CHIP PROCESSING DEVICE AND METHOD FOR CHIP PROCESSING USING THE SAME

摘要

The present invention provides a chip processing device and a method for chip processing using the same, where the device can program, detect, reset or inspect a plurality of chips, and meanwhile has one or more functions of programming, detecting, identifying, resetting or inspecting. The plurality of chips has different communication interfaces, and/or uses different communication protocols. The chip processing device can be configured to program, detect, identify, reset or inspect a chip after obtaining the model of the chip to be processed, thus having higher universality.

主权项

1. A chip processing device, comprising:
a main unit and a test head; wherein the main unit comprises a storage module, a processing module, an input/output module and an interface module; the storage module is stored with a plurality of chip models, communication protocols corresponding to the plurality of chip models, and information about a plurality of processing modes of the chip processing device, the plurality of processing modes at least comprises a inspection mode; the input/output module is configured to input a processing mode of a to-be-processed chip, input a chip model of the to-be-processed chip, or output a processing result; the processing module is configured to acquire a communication protocol corresponding to the to-be-processed chip in the storage module according to the chip model of the to-be-processed chip as input by the input/output module or a chip model acquired by identifying the to-be-processed chip; and control the test head to perform a processing treatment corresponding to the processing mode input by the input/output module to the to-be-processed chip according to the communication protocol corresponding to the to-be-processed chip; the interface module is configured to perform communication connections with the test head; the test head comprises a communication interface and a test interface, wherein: the communication interface is configured to perform communication connections with the interface module of the main unit; the test interface is configured to perform communication connections with the to-be-processed chip.