发明名称 Security method and system for an integrated circuit, particularly a memory
摘要 <p>The method involves applying electrical signals (IS0 - ISm) each representing a state of one of selected memory cells to memory cell read circuits supplying a binary output signal representing state of the cell to which it is linked. A rule to allocate the signals to the circuits is modified by applying a permutation to a part of the signals, so that each read circuit processes electrical signals of different ranks during different reading cycles. The rule is randomly or pseudo-randomly modified for every T reading cycles, where T is a constant or a variable integer greater than or equal to 1. An independent claim is also included for a memory comprising memory cells.</p>
申请公布号 EP1748444(A1) 申请公布日期 2007.01.31
申请号 EP20060014468 申请日期 2006.07.12
申请人 STMICROELECTRONICS SA 发明人 LISART, MATHIEU;DEMANGE, NICOLAS
分类号 G11C7/24;G11C7/10 主分类号 G11C7/24
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