| 摘要 |
A synchronous multi-purpose counter is provided including a plurality of counter stages. Each stage comprises J-K flipflop, for example, at least two operational gates and a switching gate. The second and subsequent stages are each additionally associated with an auxiliary gate. In each of the counter stages, the output of the plurality of operational gates is connected with the J input terminal of the flipflop while the switching gate is opened by a signal representing other than a counting operation for supplying an inverted signal of the input signal to the J input terminal to the K input terminal. A counting operation signal opens the auxiliary gate associated each counter stage to supply a signal of the same polarity as the input signal to the J input terminal to the K input terminal. The flipflop of each stage has a clock terminal C which is supplied with a clock signal. In an addition or up-counting operation, the output from the Q output terminal of each flipflop is supplied to the operational gate in all of subsequent stages which is opened by an addition operation signal. During a subtraction or down-counting operation, the output from the Q output terminal of each flipflop is supplied to the operational gate in all of subsequent stages which is opened by a subtraction operation signal. In a presetting operation, a preset operation signal opens an operational gate associated with each counter stage to supply data which is to be entered into that stage to the J input terminal thereof. In an advance shift register operation, the output from the Q output terminal of each flipflop is supplied to the operational gate associated with the next stage which is opened by a shift register operation signal. When producing a complement data, the output from the Q output terminal of a flipflop is supplied to the operational gate of that stage which is opened by a complementing operation signal.
|
