发明名称 Synchronization of digital circuits by bus triggering
摘要 Data flow between multiple digital circuits having various internal clock rates is controlled by an asynchronous trigger bus. A trigger pulse is generated on the trigger bus when a trigger condition is simultaneously detected in two circuits desiring to communicate.
申请公布号 US4017740(A) 申请公布日期 1977.04.12
申请号 US19750573298 申请日期 1975.04.30
申请人 HEWLETT-PACKARD COMPANY 发明人 FARNBACH, WILLIAM A.;SMALL, CHARLES T.
分类号 G06F13/42;(IPC1-7):H03K19/08;H03K5/13 主分类号 G06F13/42
代理机构 代理人
主权项
地址