Method and apparatus for controlling a multiprocessor system

摘要

A multiprocessor system having a computer poller and a memory poller for controlling information transfer over a time multiplex bus between a plurality of computers and an interleaved memory comprising a plurality of sections. Each poller comprises a counter and a clock so that as the counter is incremented by the clock, each computer or memory section, respectively, is sequentially interrogated to determine whether or not it requires access to a memory or computer, respectively.