| 摘要 |
A phased, four-output clock generator implemented on-chip with MOSFETs, has two phased inputs phi A and phi B thereto. If phi A and phi B are properly time-phased (in sequence: phi A=1, phi B=0; phi A=0, phi B=0; phi A=0, phi B=1; and phi A=0, phi B=0) the four outputs are time phased as: } phi 1 phi 2 phi 3 phi 4 }t1 1 0 0 0 }t2 0 1 0 0 }t3 0 0 1 0 }t4 0 0 0 1 } The clock includes two timers each of which contains a phasing module and a NOR-gate. The phasing modules have two inputs A and B and produce an output as follows: }A B Output }0 0 P }0 1 0 }1 0 1 }1 1 0 } where "P" indicates that the last succeeding output is left unchanged or stretched. The NOR-gate inputs are respectively connected to their phasing module outputs and to the B input of their corresponding phasing module. phi A is connected to the A input of the first timer and to B of the second; phi B is complementarily connected. phi 1 is derived from the A input of the first timer; phi 2 from the second timer NOR output; phi 3 from the B input of the first timer; and phi 4 from the first timer NOR output.
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