发明名称 |
Multiprocessor system having mutual exclusion control function. |
摘要 |
<p>A multiprocessor system includes a plurality of processors (10-1 to 10-N) which are respectively connected to a memory device (3) and each of which produces a first control signal when executing a test-and-set instruction and a second control signal after executing a sequence of queuing steps. The multiprocessor system further has flip-flop circuits (12-1 to 12-N) each of which is set in response to the first control signal from the corresponding one of the processors (10-1 to 10-N) and which are commonly reset in response to a second control signal from any one of the processors (10-1 to 10-N). The processors (10-1 to 10-N) are prevented from executing the test-and-set instruction while the corresponding one of the flip-flop circuits (12-1 to 12-N) is set.</p> |
申请公布号 |
EP0086601(A2) |
申请公布日期 |
1983.08.24 |
申请号 |
EP19830300556 |
申请日期 |
1983.02.03 |
申请人 |
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA |
发明人 |
MAEDA, AKIRA |
分类号 |
G06F12/00;G06F9/46;G06F9/52;G06F13/16;G06F13/18;G06F15/16;G06F15/167;G06F15/177;(IPC1-7):06F13/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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