| 摘要 |
PURPOSE:To ensure the effective transfer of data, by dividing the transfer data into plural parts to transfer them with intervals and making it possible to transmit other digital signals during said intervals. CONSTITUTION:A block length register 15, a block length counter 16, an interblock transfer queuing time register 18 and a queuing time counter 19 for plural divided data are provided into a data transfer circuit 4. These registers and counters are controlled by a DMA controlling circuit 12. In addition, a transferer address counter 7, a transfer destination address counter 8, a selector 9 and a data buffer 10 are provided. Signals 5 and 6 which occupy a bus 3 are exchanged between the circuit 4 and a CPU1, and a desired transfer data is read out of a memory 2 and set to the register 10. Then the contents of the counter 8 and the buffer 10 are sent to the bus 3. The transfer of these data are divided by the circuit 12 with time intervals, and meanwhile the bus 3 is occupied for other purposes. In such a way, the transfer efficiency can be improved. |
