发明名称 MULTILEVEL INTEGRATED CIRCUIT PACKAGING STRUCTURE
摘要 A multi-level integrated circuit packaging system having a primary support frame, an array of secondary support frames mounted in said primary support frame and an array of single chip carriers associated with each secondary support frame. An integrated circuit is encapsulated in each single chip carrier, which may be a variety of carrier types which has an insulated wiring pattern with EC wells and delete lands. The secondary and primary support frames also have EC pads so that a change capability exists to any electrical signal path terminating on the chip.
申请公布号 JPS5914660(A) 申请公布日期 1984.01.25
申请号 JP19830085186 申请日期 1983.05.17
申请人 INTERN BUSINESS MACHINES CORP 发明人 MARIO II ETSUKAA;REONAADO TEI ORUSON
分类号 H01L23/52;H01L23/40;H01L23/538;H01L25/00 主分类号 H01L23/52
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