发明名称 |
Device for testing a circuit comprising sequential and combinatorial logic elements |
摘要 |
A device for processing digital signals includes combinatorial and sequential logic elements. For the testing of the device, a shift register can be formed from the sequential elements. A test pattern is applied thereto. The result of the processing of the test pattern is applied to the shift register. The output of the shift register is connected to a second shift register which forms a moving multibit sum pattern from a received series of result patterns by way of a feedback circuit to at least one Exclusive-OR-element. An output of the feedback circuit is connected to an input of the first shift register in order to apply a subsequent test pattern thereto. After completion of the test, the sum pattern formed is checked.
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申请公布号 |
US4435806(A) |
申请公布日期 |
1984.03.06 |
申请号 |
US19810282625 |
申请日期 |
1981.07.13 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
SEGERS, MARINUS T. M.;NIESSEN, CORNELIS;KUIPER, KRIJN |
分类号 |
G01R31/28;G01R31/3183;G06F11/22;G06F11/27;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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