CMOS single chip microprocessor.

摘要

A CMOS single chip microprocessor comprises an oscillator (62) and a timing generator (60) for allowing internal circuits to periodically execute program processings in response to an operation control signal (HOLD) having a fixed cycle period. To reduce electric power consumption, command signals (COM1 to COM4) are generated after the execution of each program processing, and a circuit means (53 to 59, 68 to 72) is provided which causes the oscillator (62) and the timing generator (60) to become inoperative in response to the command signals (COM1, COM2) regardless of the level of the operation control signal, and restarts the operations of the oscillator and the timing generator in response to the transition from a first level to a second level of the operation control signal.