| 摘要 |
PURPOSE:To speed up processing speed and to simplify the constitution of the titled filter by using a ratio of a sampling period to a time constant as a specific value and multiplying the difference between an input signal and an output signal by the specific value through a shift register shifting by N digits. CONSTITUTION:An input signal from a terminal 1 is applied to an adder 4 through a sampling circuit 2 and an AD converter 3. The adder 4 finds out the difference between an output signal in of the converter 3 and an output signal on from a delay circuit 8 and applies the difference to the shift register 10. The register 10 shifts the set up difference in the register 10 to the right by N specified by a shifting number specifying circuit 11 and multiplies said difference by 1/2N. An adder 7 adds the multiplied value from the register 10 to the output signal of the circuit 8 and applies the added value to the circuit 8. If the sampling period is DELTAt, a low pass filter with time constant T=DELTAtX2N can be obtained. Thus, the digital filter with improved processing speed can be obtained. |
