| 摘要 |
An FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one embodiment, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. The FET is fabricated by forming an oxide mask (e.g., by etching a window in the gate oxide over the device active area); enhancement implanting the substrate through the window (e.g., n-substrate and n-implant for a p-channel FET); enlarging the window width a predetermined distance by etching; and depletion implanting the substrate through the window (p-implant for n-substrate) to a concentration below that of the enhancement implant. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels. This effectively provides an enhancement FET which is in parallel with a depletion FET. The effective channel width of the depletion FET equals the combined width of the two narrow depletion regions and is approximately equal to the difference in width of the two etch-defined windows. The method is applicable to both silicon and metal gate technology, to n-channel and p-channel, and to various combinations of enhancement and/or depletion devices.
|
