| 摘要 |
PURPOSE:To arrange optionally an input/output circuit section by providing a latch circuit for address designation to an input/output unit. CONSTITUTION:The input unit 2 and the output 3 are connected to an operation control unit 1 for various control via connectors A-C, and the units 2, 3 are provided with 1-bit latch circuits 23, 33. A clock line is connected in common to the latch circuit 23, 33 and a selection signal by a selection line 18 from the operation unit 1 is latched in synchronizing with the clock signal. Furthermore, the reset line 6 is connected in common and the latch content is reset at application of power or the like. The write/read operation is conducted between the input/ output units 2, 3 and a data memory section 13 ahead the logical operation and since the signal for selecting each unit is transmitted serially via the latch circuits 23, 33, the units 2, 3 are selected surely in order.
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