发明名称 CLOCK INTERRUPTION DETECTING CIRCUIT
摘要 PURPOSE:To supervise many clocks at the same time with a few monostable multivibrators by forming the titled circuit with a multi-input AND gate, a multi-input OR gate, monostable multivibrator circuits and an AND gate. CONSTITUTION:When any of input clocks from signal lines 11-14 is interrupted and goes to an L or H level, an output of the AN0d gate 15 or the OR gate 16 goes respectively to L or H. Thus, any of outputs of the two monostable multivibrators 2 goes to L and an output of an AND gate 17 goes to L. Thus, the interruption of the input clock is detected. Then even when many clocks are supervised at the same time, it is conducted with a few monostable multivibrators without preparing many monostable multivibrators.
申请公布号 JPS6184111(A) 申请公布日期 1986.04.28
申请号 JP19840205838 申请日期 1984.10.01
申请人 NEC CORP 发明人 NAKANISHI YOSHINOBU
分类号 G06F1/04;H03K5/19 主分类号 G06F1/04
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