| 摘要 |
PURPOSE:To constitute easily a decoder for double error correction 3-bit error detection DEC-TED BCH code by adding an error discrimination circuit to a known decoder for double error correction DEC BCH code. CONSTITUTION:An output of an OR circuit 5 goes to logical 1 when a single or a double error exists, because an output of a ZD4 goes to logical 1 with S<3>1+S3=0 and then with Z=S0(S<3>1+S3)=0, an output of an AND circuit 10 goes to logical 0 and an error correction signal is fed to an AND circuit 9. In case of a triple error, Z is logical 1 and an output of the OR circuit 5 is logical 0, then an output of the AND circuit 10 goes to logical 1 to detect the error. In order to correct the error, all elements are substituted in an equation 1 and whether or not each of them is a root is checked in parallel. S1alpha<2i> is obtained from S1alpha<2i>6 and S<2>1alpha<i> is obtained from S<2>1alpha<i>7 and a CI8 detects whether or not the sum of both is S<3>1+S3, and an output of the CI8 and an error correction signal are inputted to the AND circuit 9. A location where its output signal is logical 1 indicates the error location.
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