| 摘要 |
PURPOSE:To secure the number of times of the minimum refreshing cycle necessary to a dynamic RAM without stopping a CPV for a long time by counting the number of the machine cycle in which one refreshing is necessary and stopping a final machine period CPV at the time of necessities. CONSTITUTION:A counter 1 reset, when a dynamic RAM (DRAM) selecting signal is not generated from an address decoder 1, counts the number of the machine cycle of CPV where one refreshing is necessary, arrives at the number of the machine cycle, and then, a CPV stop requesting signal is generated. In response to the signal, a CPV stop confirming signal is supplied through an or gate 13, a refreshing pulse is generated from a refreshing pulse generating circuit 2, at the final machine cycle a CPU is stopped and refreshed. The counter 11 refreshed by a machine cycle before the final value reaches is reset. Thus, without stopping the CPU for a long time, the minimum refreshing cycle necessary to a DRAM can be secured.
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