| 摘要 |
PURPOSE:To increase the noise margin in a multivalued signal identification apparatus with effectively adjusting DC offset by using a reversible counter in place of an analog integrating circuit and adding a fixed value to a full adder in an asynchronizing time. CONSTITUTION:An octenary signal is inputted from an input terminal 1 and the output of an A/D converter 3 is inputted to a reversible counter 10 of eight stages which is prepared to integrate a high-order fourth bit in its output through a full adder 9. In a synchronizing state, so that '1' is inputted to a monitor terminal 11, the reversible counter 10 is counted down when the value of the high-order fourth bit is '1', meanwhile, when it is '0', the counter 10 is operated to count up. On the other hand, in an asynchronizing state, so that the signal of '0' is inputted to an asynchronous detecting monitor 11, the input of a clock to the counter is terminated and the operation of the counter is actually terminated and therefore, the data just before the asynchronizing time is added to the full adder 9 as a fixed data.
|
