发明名称 CONTROL SYSTEM FOR CONTROL MEMORY ADDRESS
摘要 PURPOSE:To attain a fault processing system with simple constitution by storing previously plural firm ware entry addresses into a part of an address stack for execution of the fault processing and designating an entry address of the firmware when the fault is detected to perform the corresponding fault processing in response to the pulse width of the fault detecting signal. CONSTITUTION:When a fault is detected by a fault detecting means (not shown here), the contents of the fault are set and then supplied to a fault entry address control circuit 10. The circuit 10 can designate the entry address corresponding to each fault and therefore controls the pulse width of the fault detecting signal in response to the type of the fault processing to supply this signal to a stack pointer register 51. As a result, the value of the register 51 is increased and reduced with reference to the pointer where the entry address of the microprogram corresponding to the fault of an address stack 4.
申请公布号 JPS62100836(A) 申请公布日期 1987.05.11
申请号 JP19850240865 申请日期 1985.10.28
申请人 NEC CORP 发明人 TANIMOTO KENZO
分类号 G06F9/22 主分类号 G06F9/22
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