| 摘要 |
PURPOSE:To shorten a stabilizing time and to obtain an accurate frequency by PLL-locking a synchronizing signal of PAL system and a subcarrier frequency by means of horizontal synchronization. CONSTITUTION:An oscillator 1 oscillates at a frequency (n)XfH which is (n)-times of a horizontal synchronizing signal, and its output is frequency-divided by a frequency divider 3 for generating synchronizing signal. Thus a horizontal synchronizing signal is generated as the synchronizing signal, and supplied to a phase comparator 6. An oscillator 2 oscillates at a frequency (mXfsc) of m-times (for instance four times) of a color subcarrier signal, whose oscillating output is supplied to a variable frequency divider 4. The output of the frequency divider is supplied to the phase comparator 6 and further to a frequency divider 5 for control. The output of the frequency divider 5 is badback to the frequency divider 4, which, normally, has a division ratio of a1 and generates a pseudo horizontal synchronizing signal A, but in case a division ratio controlling signal B is supplied from the frequency divider 5, the ratio comes to a2. Consequently, the signal A is phase-compared with the horizontal synchronizing signal from the frequency divider 3. Therefore, by controlling the oscillator 1 or 2, the PLL can be formed.
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