| 摘要 |
PURPOSE:To reduce the circuit scale while number of n-bit register array into a half by converting contents of a shift register into a prescribed replacement pattern and sharing it to two channels of bipolar circuits. CONSTITUTION:An n-set of consecutive '0' patterns of a binary code are inputted to an n-bit shift register SR1 and when the state of each SR 11 is all zero, the output of the (n) consecutive '0' detector 2 goes to '1'. and a replaced code pattern of a BnZS code is shifted in place of the n-set of consecutive '0' patterns via each selector 12 of the SR1 by using a load pulse of a LOAD generation FF 5. Moreover, the 1 level of the output of the detector 2 is held in a count state hold circuit 6 at the leading of the clock inverted by the inverter 7, an n-counter 4 is operated and the circuit 6 is reset at the end of count. The FF 31 of the bipolar rule converter 3 at the succeeding position is subject to toggle operation at each clock at n-count of the counter 4 to share the replaced pattern alternately to the bipolar two-channel independently of '0', '1'.
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