发明名称 COMPOSING DEVICE FOR LOGIC CIRCUIT
摘要 PURPOSE:To reduce calculation time required for processing by forecasting cost required for the conversion of an answer and excluding useless search. CONSTITUTION:Although a state partially converted into a physical circuit on the way of conversion from logic circuits to physical circuits, the forecasted value of cost required for the conversion of all branch nodes of respective nodes (n) under said status into physical circuits is set up as a label of the nodes (n). The sum of the labels to be the set of nodes to be converted is calcu lated and the sum of the calculated value and the cost of the converted physical circuits is set up as the forecasted value of the converted cost of all the circuits. When the forecasted value is < than the cost of the best answer obtained up to the time, the preceding conversion is continued from the current state, but in the other case, the current state is returned to the immediately preceding state to search another probability. Since the cost of the converted result is forecasted at each point of time and useless conversion is excluded, an optimum answer can be detected within a short calculation time.
申请公布号 JPS63143673(A) 申请公布日期 1988.06.15
申请号 JP19860290879 申请日期 1986.12.05
申请人 NEC CORP 发明人 YOSHIMURA TAKESHI
分类号 G06F17/50 主分类号 G06F17/50
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