发明名称 Resilient bus system
摘要 A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
申请公布号 US4764862(A) 申请公布日期 1988.08.16
申请号 US19850717201 申请日期 1985.03.28
申请人 HONEYWELL BULL INC. 发明人 BARLOW, GEORGE J.;KEELEY, JAMES W.
分类号 G06F11/00;G06F13/42;(IPC1-7):G06F13/14 主分类号 G06F11/00
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