发明名称 PICTURE SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To reduce the width of a picture pattern, and to elevate a horizontal resolution by detecting the horizontal edge of the picture pattern from the read-out output of a picture memory, and delaying the detected horizontal edge by a period, which is shorter than a time width corresponding to the dot of the minimum width, determined by the storage capacity of the picture memory. CONSTITUTION:A width reducing means to reduce the width of the picture pattern is provided. The width reducing means consists of a vertical line detection circuit 12, which extracts only a vertical line among a cross hatch pattern, a vertical line erasure circuit 13, which erases the detected vertical line from the cross hatch pattern, a vertical line width reduction circuit 14, which generates the vertical line which has a narrower width than that of the detected vertical line, while holding a leading edge in common together with it, from the detected vertical line, and an addition circuit 15, and it successively reads out the picture data, stored in the picture memory 2, while conforming it to a deflection scanning, and forms the picture pattern which is the aggregate of the dots having the minimum width, determined by the storage capacity of the picture memory 2, and at the same time, detects the horizontal edge of the picture pattern from the read-out output of the picture memory 2, and reduces the picture pattern width by delaying the detected horizontal edge by the shorter period than the time width corresponding to the dot of the minimum width.
申请公布号 JPS63211994(A) 申请公布日期 1988.09.05
申请号 JP19870044599 申请日期 1987.02.27
申请人 NEC HOME ELECTRONICS LTD 发明人 ARA KOICHI
分类号 H04N17/00;G09G1/16 主分类号 H04N17/00
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