SYNCHRONIZING SIGNAL GENERATING CIRCUIT

摘要

The circuit for recognising the start point of the data status signal applied to a decoder circuit sequentially comprises an inverter (I1) receiving data enable signal, a flip-flop (FF1) providing output to AND gate (A1) and flip-flop (FF2). The output (Q) of the flip-flop (FF2) is provided to the AND gate (A1) so that the block synchronous signal is generated.