| 摘要 |
PURPOSE:To minimize the length of a clock signal wiring, and enable easily the constitution of an integrate circuit of high speed and high performance, by arranging fixedly F/F cells and C/D cells, and mounting them in the same cell row. CONSTITUTION:Flip flop cell row 30 comprises flip flop (F/F) cells 40 and clock distributer (C/D) cells 50 whose position relations are mutually fixed. Wiring regions 60 are arranged along the side of the F/F cell row 30. Clock signal wirings 70 constitute, in the wiring region 60, wirings between the F/F cells 40 and the C/D cells 50. That is, the C/D cells 50 are arranged in the central part of the F/F cell raw 30, and wire the F/F cells 40 and the C/D cells 50 on a line of the shortest distance. Thereby, the wiring length is reduced to a minimum, so that the circuit operates at a high speed. Further, the wiring length becomes uniform, and clocks skew can be decreased, so that an integrated circuit with high performance can be obtained.
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