| 摘要 |
A static row driver for an array of memory cells which includes a plurality of NAND gates each having a pair of row line driver input signals, an inverter coupled to an output of each of the NAND gates, a switch coupled to an output of each of the inverter circuits and a switch control coupled to each of the switches for opening an associated switch and passing the signal from a corresponding inverter output to an associated row line.
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