| 摘要 |
PURPOSE:To decrease a phase difference between specified signals and to enable an integrated circuit of this design to operate through the correct signals at a high speed by a method wherein the wirings of a specified signal provided between a specified terminal and an input drive circuit and an inner drive circuit are made equal to each other in length. CONSTITUTION:Clock signals different from each other in phase arc wired from bonding pads 2 and 3 to clock buffers 6 and 7 through wirings 4 and 5 and to clock drivers 10 and 11 through wirings 8 and 9, and the output of the clock drivers 10 and 11 is fed to a functional block cell 13. And the wirings 4 and 5, and 8 and 9 are all equal to each other in length, and the buffers 6 and 7 and the drivers 10 and 11 constitute the same wiring circuit, and arranged at fixed positions and wired through fixed wirings on an LSI master. Therefore, the signals from the pads 2 and 3 to the drivers 10 and 11 are equal to each other in lag, so that the clock skew between clocks different from each other in phase can be eliminated. By these processes, an LSI can be operated through a correct signals at a high speed. |
