SHIFT REGISTER UNIT, DISPLAY PANEL AND DISPLAY APPARATUS

摘要

A shift register unit includes a latch circuit and a transmission circuit. The latch circuit is configured to process a clock signal received by its first clock signal end and a low level signal by a NOR operation to obtain a signal and output the obtained signal when a selection signal is of a high level; during a first time period where the selection signal is of a low level, process a signal outputted by the latch circuit when the selection signal is of a high level by a NOT operation, then process the resultant signal with a feedback signal by a NOR operation to obtain a signal and output the obtained signal; output a low level signal during a time period where the selection signal is of a low level other than the first time period. The transmission circuit is configured to output a signal related to the clock signal received by its first clock signal end when the signal outputted by the latch circuit is of a high level; and output a corresponding signal when the signal outputted by the latch circuit is of a low level.

主权项

1. A shift register unit, comprising:
a latch circuit, configured to
process a clock signal received by a first clock signal end of the shift register unit and a low level signal by a NOR operation to obtain a signal, and output the obtained signal, during a time period where a selection signal is of a high level, wherein the clock signal received by the first clock signal end is of a low level when the selection signal is of a high level;process the signal outputted by the latch circuit when the selection signal is of a high level by a NOT operation, then process the resultant signal with a feedback signal by a NOR operation to obtain a signal, and output the obtained signal, during a first time period where the selection signal is of a low level; andoutput a low level signal, during a time period where the selection signal is of a low level other than the first time period where the selection signal is of a first low level; and a transmission circuit, configured to
output a signal related to the clock signal received by the first clock signal end when the signal outputted by the latch circuit is of a high level; andoutput a corresponding signal when the signal outputted by the latch circuit is of a low level; wherein, the feedback signal is able to make the signal outputted by the latch circuit during the time period where the selection signal is of a high level and the signal outputted by the latch circuit during the first time period where the selection signal is of a low level be the same; the feedback signal is converted from being of a low level to being of a high level, at an end time point of the first time period where the selection signal is of a low level; and the first time period where the selection signal is of a low level is a time period from a time point when the selection signal is converted from being of a low level to being of a high level to a time point when a signal outputted by a next stage shift register unit with respect to the shift register unit jumps from being of a low level to being of a high level.