发明名称 OPERATING STATE ANALYZER FOR PARALLEL COMPUTER
摘要 <p>PURPOSE:To obtain an operating state analyzer for a parallel computer which analyzes the operating state of each cell when an optional parallel program is carried out and displays the analyzing, result in an easy-to-understand way by collecting the data on the operating states stored in each cell at a host. CONSTITUTION:A parallel program 14 is processed at a parallel processing part 2. Each of cells 7-12 contains a processor and an internal memory and write successively the data on the operating state of Y in a processing state of the program 14. When the processing of the program 14 is complete, a host 6 collects the data written in the internal memories of the cells 7-12. Then the necessary one of these collected data is extracted and shown by a display mechanism 3. Based on these displayed data, the operating states of many cells can be easily grasped. Then the program 14 is improved with high efficiency so that the program 14 is debugged and the parallel processing speed is increased.</p>
申请公布号 JPH0535704(A) 申请公布日期 1993.02.12
申请号 JP19910150265 申请日期 1991.06.21
申请人 FUJITSU LTD 发明人 IGAWA HIDEKO
分类号 G06F3/14;G06F3/048;G06F11/32;G06F15/16;G06F15/177;G06F15/80 主分类号 G06F3/14
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