发明名称 Complementary MISFET voltage generating circuit for a semiconductor memory
摘要 A voltage generating circuit having a voltage dividing circuit of complementary MISFETs is provided in an arrangement wherein a controlled output voltage, such as a bias voltage applied to plate electrodes of storage cells in a RAM, is obtained. The voltage dividing circuit has a series arrangement, between the power source voltage and a predetermined voltage, such as ground potential, of a first resistance, a first diode-connected MISFET, a second resistance and a second diode connected MISFET. Also, the voltage generator circuit has a first output MISFET of a first channel conductivity type having its gate coupled to the common connection of the first diode-connected MISFET and first resistance as well as a second output MISFET of the second conductivity type in series therewith which has a gate coupled to the common connection of the second diode-connected MISFET and second resistance. The first and second output MISFETs have their drains respectively coupled to receive the power source voltage and predetermined voltage and the source of the first output MISFET is coupled with the source of the second output MISFET wherein an output voltage of about 1/2 the potential of the power source voltage is obtained.
申请公布号 US5187685(A) 申请公布日期 1993.02.16
申请号 US19910749851 申请日期 1991.08.26
申请人 HITACHI, LTD. 发明人 SATO, KATSUYUKI;KAWAMOTO, HIROSHI;YANAGISAWA, KAZUMASA
分类号 G11C11/4074;G11C29/50 主分类号 G11C11/4074
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