| 摘要 |
PURPOSE:To perform O-cutting/1-raising rounding processing of the positive- negative symmetry at a high speed. CONSTITUTION:A 1st decoder 21 inputs a 2nd input signal 12 and outputs the 1st and 2nd decoding signals 13 and 14. A selection circuit 23 outputs the signal 13 as an output signal 16 when the most significant bit 15 showing the code of a 1st input signal 11 is equal to '0' and outputs the signal 14 as the signal 16 when the bit 15 is equal to '1', respectively. An arithmetic logical operation circuit 24 adds both signals 11 and 16 together and outputs this addition result as an output signal 18. A 2nd decoder 22 inputs the signal 12 and outputs a 3rd decoding signal 17 in response to the value of a prescribed table. Then, a mask circuit 25 secures the AND of the signal 17 with the signal 18 and outputs the rounding result as an output signal 19. |
