| 摘要 |
<p>PURPOSE:To adjust a phase of a clock signal having a frequency being a multiple of (n) of that of preamble bits to an optimum phase in the detection of frame synchronization of a burst signal having the preamble bits and frame bits. CONSTITUTION:A consecutive change point detection pulse 10 obtained by detecting consecutive change points of a reception burst signal 1 and a consecutive pattern detection pulse 14 obtained by detecting consecutive preamble bits having a duty ratio of 50% are NANDed and a coincident pulse 16 is generated. Then a clock signal 12 is loaded in a timing of the coincident pulse 16, the phase is controlled to detect a frame of the reception burst signal 1.</p> |
