| 摘要 |
A data processing apparatus is provided which includes an instruction decoder, an input circuit, an input selecting circuit, a plurality of arithmetic logic circuits, an output selecting circuit, and an output circuit. The input circuit receives input data to provide a plurality of data signals. The input selecting circuit selects the data signals to distribute each of them to corresponding one of the arithmetic logic circuits according to a command from the instruction decoding circuit. The arithmetic logic circuits receive the data signals to perform arithmetic and logic operations and to provide operation output signals indicative of results of the arithmetic and logic operations. The output selecting circuit selects the operation output signals to distribute each of them to a given location of the output circuit. This architecture of the data processing apparatus allows a plurality of arithmetic and logic operations to be executed at high speed using the single input and output circuits. <IMAGE> |
