SPACER CHAMFERING GATE STACK SCHEME

摘要

A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

主权项

1. A method of forming a gate structure for a semiconductor device comprising:
epitaxially forming a semiconductor material on the source and drain region portions of fin structures; forming first spacers on sidewalls of replacement gate structures that are present on the fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structures, wherein forming said first spacers comprises conformally depositing a dielectric material on horizontal and vertical surfaces of the replacement gate structures and the fin structure, and etching the dielectric material to remove the dielectric material that is present on the horizontal surfaces; forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structures; and substituting the replacement gate structures with functional gate structures having a first width portion in a first space between said first spacers, and a second width portion having a second width in a second space between said second spacers, wherein the second width portion is greater than the first width portion.