| 摘要 |
PURPOSE: To provide an oscillation circuit used for an APC (PLL) circuit or the like with a short lock time and a small circuit scale. CONSTITUTION: In a digital oscillation circuit 11, a crystal 13 is connected to an analog system clock generating circuit 12 to generate a master clock fCLK. An analog control signal is given to a clock generating circuit 12 from a frequency control terminal 14. The clock fCLK is fed to a digital oscillator 15, from which an oscillation signal fsc is obtained at an output terminal 16. A switching control signal is given to a control terminal 17 of the digital oscillator 15 so as to select an oscillation signal fsc corresponding to the television system. Since the clock fCLK is changed analogically to obtain a desired frequency, it is not required to take bit resolution in the oscillation circuit 11 into account and an event of one-bit vibration is not caused and a problem of a color phase shift detection limit at the end of one line is not caused. |
