Timing recovery for digital receiver with interleaved analog-to-digital converters

摘要

A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.

主权项

1. A receiver comprising:
a first analog to digital converter (ADC) circuit to convert an analog input signal into first digital samples under control of a first sampling clock; a first clock generator circuit to adjust a phase of the first sampling clock based on one or more first phase control signals; a second ADC circuit to convert the analog input signal into second digital samples under control of a second sampling clock; a second clock generator circuit to adjust a phase of the second sampling clock based on one or more second phase control signals; a decision circuit to recover data based on the first digital samples and the second digital samples; and feedback circuitry to generate the one or more first phase control signals for the first clock generator circuit based on the recovered data and to generate the one or more second phase control signals for the second clock generator circuit based on the one or more first phase control signals.