Semiconductor device and structure

摘要

A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a Phase-Lock-Loop (PLL) circuit, where the Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, and where the least one input structure is designed to connect an input to the device from external devices.

主权项

1. A 3D semiconductor device, comprising:
a first layer comprising first transistors; a second layer overlying said first transistors and comprising second transistors;
wherein said second layer comprises a first through layer via with a diameter of less than 150 nm and a second through layer via,wherein said second through layer via is part of a heat removal structure of said device; and a Phase-Lock-Loop (PLL) circuit,
wherein said Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, andwherein said least one input structure is designed to connect an input to said device from external devices.