| 摘要 |
<p>PURPOSE: To improve the reliability of an equipment operation while reducing the load of a CPU by generating reset signals for setting respective parts including the CPU to an initial state when the abnormality of the input interval of input signals is detected. CONSTITUTION: The counter of first-third judgement circuits 21-23 constitutes an abnormality detection means for inputting signals CS1-CS3 relating to the output of information for driving an object to be controlled periodically supplied from the CPU 1 to the prescribed object to be controlled (a ROM 2, a RAM 3 and a display driver 28) and detecting the abnormality of the input intervals of the input signals CS1-CS3. Also, a JK flip constitutes a reset signal generation means for generating the reset signals RSTO for setting the respective parts including the CPU 1 to the initial state when the abnormality of the input intervals of the input signals CS1-CS3 is detected. Then, by resetting the respective parts including the CPU 1 to the initial state at the time of the abnormality due to the abnormal loop or runaway of a program, the reliability of the equipment operation is improved.</p> |
