发明名称 ON-CHIP VACUUM PACKAGE TECHNOLOGY FOR MICROMECHANICAL DEVICES
摘要 <p>A process for manufacturing a vacuum enclosure for a semiconductor device formed on a substrate with leads extending peripherally, and the product manufactured by the process. In a first embodiment, an intrinsic silicon shell (10) is sealed to the substrate (12) via electrostatic or anodic bonding with the leads (16) diffusing into the shell. In a second embodiment, a thin interface layer (18') of silicon or polysilicon is deposited on the substrate (12') prior to electrostatic bonding a glass shell (10') thereon. In a third embodiment, tunnels (30'') are formed between a lower peripheral edge of the shell (10'') and the substrate (12''), allowing leads (16'') to pass thereunder. The tunnels are sealed by a dielectric material (14'') applied over the enclosure.</p>
申请公布号 WO1997003459(A1) 申请公布日期 1997.01.30
申请号 US1996011415 申请日期 1996.07.08
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