| 摘要 |
<p>A field emitter device formed by a veil process wherein a protective layer including a release layer is deposited on a gate electrode layer (62) for the device, the protective layer overlaying the circumscribing peripheral edge of the opening of the gate electrode layer (62) to protect the edge of the gate electrode layer (62) during etching of a field emitter cavity (72) in a dielectric material layer (30) on a substrate (12) and during the formation of a field emitter element (40) in the cavity by depositing a field emitter material through the opening (72). The protective layer is readily removed subsequent to completion of the cavity etching formation steps, to yield the field emitter device. The field emission device further includes a current limiter composition (14) for permitting high frequency emission of electrons from the field emitter element (40) at low turn-on voltage.</p> |
