CARRY VALUE GENERATION DEVICE AND ADDITION/SUBTRACTION M BIT VALUE GENERATION DEVICE

摘要

PROBLEM TO BE SOLVED: To maintain a high data rate while reducing the circuit scale and in a two-dimensional inverse discrete cosine transformation (IDCT) circuit having parallel processing paths using distribution operation technology. SOLUTION: The parallel processing paths of DCT coefficient data are converted into even- and odd-numbered processing paths. A partial IDCT circuit executes first one-dimensional transformation in parallel in respective processing paths and DCT coefficient data becomes a parameter, and is transposed in an transposing part. Then, second one-dimensional transformation is executed and the parameter becomes a picture element value. The IDCT circuit has accumulators 120a-120d and carry logics 800a-800d. The carry logics calculate the carry value of the prescribed low bit (LSB) of a coefficient value without executing addition.