| 摘要 |
PROBLEM TO BE SOLVED: To enhance the timing accuracy by setting the number of AND and OR gates in a variable delay circuit at a constant small number regardless of the number of selection circuits thereby shortening the propagation delay time and realizing a high speed variable speed delay operation while suppressing the effect of temperature and fluctuation in the fabrication of circuit. SOLUTION: Path select signals SEL0-n-1 for selecting AND gates 0-n-1 are stored at respective addresses #0 -#n-1 of a memory in a control circuit 4 and a delay amount is constituted to be modified by varying an address signal being applied to the memory. When an AND0 is selected by a select signal SEL0, for example, the propagation delay time Dn of an input pulse from an input IN to an output OUT is equal to the sum of the propagation delay time of an AND gate and the gate delay Dr of an OR gate and the propagation delay time is equal to Dn +nDr when ANDn-1 is selected by a select signal SELn-1 . Consequently, only two gate stages are required for generating a propagation time Dn (OFFSETθTPD) when a delay amount to be added is 0 and it can be set constant regardless of the number of select path.
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