SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING ENHANCEMENT TYPE NMOS AND DEPRESSION TYPE MOS WITH N-TYPE CHANNEL IMPURITY REGION AND P-TYPE IMPURITY LAYER UNDER N-TYPE CHANNEL IMPURITY REGION

摘要

Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.

主权项

1. A semiconductor integrated circuit device, comprising:
an enhancement type first N-channel type MOS transistor comprising:
a first gate oxide film formed on a first P-type well region;a first gate electrode;a first gate terminal connected to the first gate electrode;a first source region and a first drain region, each of which comprises an N-type low concentration region and an N-type high concentration region;a first drain terminal connected to the first drain region;a first source terminal connected to the first source region; anda first body terminal connected to the first P-type well region,the first N-channel type MOS transistor having a positive threshold voltage; and a depression type second N-channel type MOS transistor comprising:
a second gate oxide film formed on a second P-type well region;a second gate electrode;a second gate terminal connected to the second gate electrode;a second source region and a second drain region, each of which comprises an N-type low concentration region and an N-type high concentration region;a second drain terminal connected to the second drain region;a second source terminal connected to the second source region;a second body terminal connected to the second P-type well region; andan N-type channel impurity region,the second N-channel type MOS transistor having a negative threshold voltage, the first gate terminal and the first drain terminal being connected to the second source terminal and the second gate terminal, the first source terminal and the first body terminal being connected to a ground potential which is a lowest potential in a circuit, the second drain terminal being connected to a power supply voltage which is a highest potential in the circuit, the second body terminal being connected to the ground potential, the second P-type well region having an impurity concentration higher than an impurity concentration of the first P-type well region, each of the second source region and the second drain region comprising an N-type low concentration region in proximity to the second gate electrode and an N-type high concentration region in contact with the N-type low concentration region, and a length of the N-type low concentration region in the second source region from an end of the second gate electrode to the N-type high concentration region being larger than a length of the N-type low concentration region in the second drain region from another end of the second gate electrode to the N-type high concentration region.