| 摘要 |
A device for digital signal processing, applied in the sphere of radio-electronics for parallel signal processing in analogue technique and parallel data processing in digital technique. The problem, concerning creating of a device for digital signal processing which scheme provides possibility for achieving maximum processing speed. The device consists of a decoder (1), connected to registers (5). The outputs of the registers (5) are three-bit and are connected to controlling inputs (10) of two-way buffers (11). The input/outputs of the peripheral two-way buffers (11) form the input/outputs (16) of the device and an operative register matrix (6) is built up. The two-way buffers (11) are forming a logical processor (12). The two-way buffers (11) could have seven states and are cross-connected to each other in the form of a three-dimensional grid. |
