发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To quickly transform an output frequency to a target frequency by outputting a pump-up or pump-down signal when the frequency division ratio of a frequency divider does not reach a specific value. SOLUTION: A voltage-controlled oscillation circuit 3 outputs an output signal fo having its oscillation frequency varied with an input control voltage. A programmable frequency divider 4 divides the frequency of the output signal fo at a specific frequency division ratio N. Then the frequency divider 4 outputs a feedback signal fo having a frequency fo/N to a phase comparing circuit 5, which compares it with the reference signal fr outputted by a reference frequency dividing circuit 1 and selects and outputs a high pump-up signal from a terminal (c) to a control circuit 6 only in a difference period of respective phases when the feedback signal fu is lagging in phase or a high pump-down signal from a terminal (d) when leading. A charge pump 7 supplies electric charges to a low-pass filter 8 with the high signal of a terminal (e) of the control circuit 6 and discharges electric charges with the high signal of a terminal (f).
申请公布号 JPH11112334(A) 申请公布日期 1999.04.23
申请号 JP19970264469 申请日期 1997.09.29
申请人 SANYO ELECTRIC CO LTD;TOTTORI SANYO ELECTRIC CO LTD 发明人 WASHIMI IKUAKI
分类号 H03L7/089;H03L7/199 主分类号 H03L7/089
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