| 摘要 |
In the bus switch system of the invention, with the adapter, the first input and first output registers in cascade connection on the data transferring bus of bus switch compose a shift register. Also, with the bridge, the second input and second output registers in cascade connection on the first data transferring bus compose a shift register. This allows data to be transferred to the adjacent adapter at one clock cycle, thereby the clock rate in data transfer is made faster. Also, the data transfer on the first and second data transferring buses is conducted in one direction and the input/output control is optimally conducted by the first and second control means. Thereby, the switch control in data transfer is made easier.
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