发明名称 TESTING CIRCUIT DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a testing circuit device for a semiconductor integrated circuit for determining whether stress impression is properly performed for a burn-in test. SOLUTION: A periodical signal S is inputted into the first stage of each scan chain, thereby shift-operating each flip-flop circuit with a scan function. As an expected output value of a flip-flop circuit located in the last stage of each scan chain, the output of a flip-flop circuit with the scan function of a scan chain having the same stage number is used, and the output of a flip-flop circuit, having a corresponding period, is used in consideration of periodicity. This enables determination of whether stress is impressed properly on an internal circuit and to output the result of it from a determination signal output terminal 407 to the exterior.
申请公布号 JP2001183425(A) 申请公布日期 2001.07.06
申请号 JP19990371085 申请日期 1999.12.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRANO KENKICHI
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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