| 摘要 |
PROBLEM TO BE SOLVED: To provide a digital DLL circuit that can utilize a wide operating frequency range even when the circuit scale is not increased. SOLUTION: The digital DLL circuit is provided with an oscillation circuit that generates internal clock signals by a number designated by a 1st control signal after an input clock signal is changed, a frequency divider circuit that frequency-divides a internal clock signal by a number designated by the 1st control signal synchronously with a change in the input clock signal to provide an output of a frequency division signal, a delay line that delays the frequency division signal by a time designated by a 2nd control signal to output an output clock signal, a clock driver that delays the output clock signal by a prescribed time to output a feedback clock signal, a phase comparator that detects a phase difference between the input clock signal and a feedback clock signal to output a phase difference signal, and a delay control circuit that adjusts the 1st control signal and the 2nd control signal to output them on the basis of the phase difference signal. |
