发明名称 |
Memory circuit having electrically programmable fuses |
摘要 |
A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially. The actual time multiplexing operation for performing the transfer is preferably enabled only after the chip power-up state. |
申请公布号 |
EP1128269(A2) |
申请公布日期 |
2001.08.29 |
申请号 |
EP20010301643 |
申请日期 |
2001.02.23 |
申请人 |
INFINEON TECHNOLOGIES NORTH AMERICA CORP.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KIRIHATA, TOSHIAKI;DANIEL, GABRIEL |
分类号 |
G11C11/413;G11C11/401;G11C29/00;G11C29/04 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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